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document number: 303110-008 intel? celeron? m processor on 90 nm process datasheet january 2007
2 datasheet iinformation in this document is provided in connection with in tel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by th is document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products in cluding liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pa tent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel? celeron? m processor may contain design defects or errors known as errata which may cause the product to deviate fro m published specifications. current characterize d errata are available on request. contact your local intel sales office or yo ur distributor to obtain the latest specifications and before placing your product o rder. intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor famil y, not across different processor families. see www.intel.com/products/processor_number for details. intel, celeron, mmx, and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be cl aimed as the property of others. copyright? 2004?2007, intel corporation. all rights reserved.
datasheet 3 contents 1introduction .............................................................................................................. 7 1.1 terminology ....................................................................................................... 8 1.2 references ......................................................................................................... 8 2 low power features ................................................................................................ 11 2.1 clock control and low power states .................................................................... 11 2.1.1 normal state ......................................................................................... 11 2.1.2 autohalt power-down state ................................................................... 11 2.1.3 stop-grant state.................................................................................... 11 2.1.4 halt/grant snoop state ......................................................................... 12 2.1.5 sleep state ........................................................................................... 12 2.1.6 deep sleep state ................................................................................... 13 2.2 fsb low power enhancements ............................................................................ 13 2.3 processor power status indicator (psi#) signal..................................................... 14 3 electrical specifications ........................................................................................... 15 3.1 power and ground pins ...................................................................................... 15 3.1.1 fsb clock (bclk[1:0]) and processor clocking ........................................... 15 3.2 voltage identification and power sequencing .... .................................................... 15 3.3 catastrophic thermal protection .......................................................................... 17 3.4 signal terminations and unused pins ................................................................... 17 3.5 fsb frequency select signals (bsel[1:0])............................................................ 17 3.6 fsb signal groups............................................................................................. 17 3.7 cmos signals ................................................................................................... 19 3.8 maximum ratings.............................................................................................. 19 3.9 processor dc specifications ................................................................................ 19 4 package mechanical specific ations and pin information .......................................... 29 4.1 processor pinout and pin list .............................................................................. 37 4.2 alphabetical signals reference ............................................................................ 55 5 thermal specifications and design considerations .................................................. 63 5.1 thermal specifications ....................................................................................... 65 5.1.1 thermal diode ....................................................................................... 65 5.1.2 thermal diode offset .............................................................................. 66 5.1.3 intel? thermal monitor........................................................................... 67
4 datasheet figures 1 clock control states .................................................................................................11 2 illustration of deep sleep state vcc static and ripple tolerances for the celeron m processor (deep sleep state): vid=1.260 v .......................................22 3 illustration of active state vcc static and ripple tolerances for the celeron m processor ulv: vid=0.940 v ............................................................24 4 illustration of deep sleep state vcc static and ripple tolerances for the celeron m processor ulv: vid=0.940 v ............................................................25 5 active vcc and icc loadline for the celeron m processor: standard voltage and ultra low voltage ......................................................................25 6 deep sleep vcc and icc loadline for celeron m processors: standard voltage and ultra low voltage ......................................................................26 7 micro-fcpga package top and bottom isometric view s .................................................29 8 micro-fcpga package - top and side views .................................................................30 9 micro-fcpga package - bottom view...........................................................................31 10 micro-fcbga package top and bottom isometric view s .................................................33 11 micro-fcbga package top and side views ...................................................................34 12 micro-fcbga package bottom view.............................................................................36 13 the coordinates of the processor pins as viewed from the top of the package ..................38 tables 1 voltage identification definition .... ..............................................................................16 2 fsb pin groups ........................................................................................................18 3 processor dc absolute maximum ratings.....................................................................19 4 voltage and current specifications..................... .........................................................20 5 voltage tolerances for the celeron m processor (d eep sleep state).................................22 6 voltage tolerances for the celeron m processor ul v (active state)..................................23 7 voltage tolerances for the celeron m processor ulv (deep sleep state) ..........................24 8 fsb differential bclk specifications ............................................................................26 9 agtl+ signal group dc specifications ........................................................................27 10 cmos signal group dc specifications................. .........................................................27 11 open drain signal group dc specifications .......... ........................................................28 12 micro-fcpga package dimensions ..............................................................................32 13 micro-fcpga package dimensions ..............................................................................35 14 pin listing by pin name .............................................................................................39 15 pin listing by pin number ..........................................................................................46 16 signal description.....................................................................................................55 17 power specifications for the celeron m processor ..........................................................64 18 thermal diode interface ............................................................................................66 19 thermal diode specification .......................................................................................66
datasheet 5 revision history revision description date -001 initial release july 2004 -002 updates include: ? document title from ?intel? celeron? m processor ultra low voltage on 90 nm process? to ?intel? celeron? m processor on 90 nm process? ? added micro-fcpga package information throughout chapter 4 ? celeron? m processor 360 and 350 dc and thermal and power specifications (updated ta b l e 4 and ta b l e 1 7 ) august 2004 -003 updates include: ? added resources to the reference table 1 ? bsel[1:] literature updated ? celeron m processor 370 and 373 dc and thermal and power specifications (updated ta b l e 4 and ta b l e 1 7 ) ? execute disable bit and le ad free feature referenced january 2005 -004 ? celeron m processor 383 dc and thermal and power specifications (updated table ta b l e 4 and ta b l e 1 7 ) april 2005 -005 ? added celeron m processor 380 specifications july 2005 -006 ? updated celeron m processor 370, 360j, 350j and celeron m processor ulv 383, 373 specifications for optimized vid (t ta b l e 4 and ta b l e 1 7 ) ? updated celeron m processor ulv 383, 373 tdp specification ( ta b l e 1 7 ) july 2005 -007 ? added celeron m processor 390 specifications january 2006 -008 ? updated celeron m 390 ther mal specifications january 2007
6 datasheet
datasheet 7 introduction 1 introduction the intel? celeron? m processor based on 90 nm process technology is a high- performance, low-power mobile processor with several enhancements over previous mobile celeron processors. throughout this document, the term celeron m processor signifies intel celeron m processor based on 90 nm technology. this document contains specification for the celeron m processor 390, 380, 370, 360j, 360, 350j, 350 and the celeron m processor ultra low voltage 383, 373, 353 . note: intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family, not across different processor families. see www.intel.com/produ cts/processor_number for details. the following list provides some of the key features on this processor: ? manufactured on intel?s advanced 90 na nometer process technology with copper interconnect. ? supports intel architecture with dynamic execution ? on-die, primary 32-kb instruction cache and 32-kb write-back data cache ? on-die 1-mb (512-kb for celeron m processor ultra low voltage 373 and 353) second level cache with advanced transfer cache architecture, 8-way set associativity and ecc (error correcting code) support. ? data prefetch logic ? streaming simd extensions 2 (sse2) ? 400-mhz, source-synchronous front side bus (fsb) ? micro-fcpga and micro-fcbga (ulv parts available only in micro-fcbga) packaging technologies (including lead free technology for the micro-fcbga package for celeron m processors 390, 380, 370, 383, 373, and 353). ? execute disable bit support for enhanced security (available on processors with cpu signature=06d8h and recommended for implementation on intel? 915/910 express chipset-based platforms only) the celeron m processor maintains support for mmx? technology and internet streaming simd instructions and full compatibility with ia-32 software. the on-die, 32-kb level 1 instruction and data caches and the 1-mb (512-kb for celeron m processor ultra low voltage 373 and 353) leve l 2 cache with advanced transfer cache architecture enable significant performa nce improvement over existing mobile processors. the processor?s data prefetch logic speculatively fetches data to the l2 cache before an l1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. the streaming simd extensions 2 (sse2) en able break-through levels of performance in multimedia applications including 3- d graphics, video decoding/encoding, and speech recognition. the new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering app lications and advanced 3-d geometry techniques, such as ray tracing. the celeron m processor?s 400-mhz fsb utilizes a split-transaction, deferred reply protocol. the 400-mhz fsb uses source-syn chronous transfer (sst) of address and data to improve performance by transferring data four times per bus clock (4x data
introduction 8 datasheet transfer rate, as in agp 4x). along with the 4x data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or 2x address bus. working together, the 4x data bus and 2x address bus provide a data bus bandwidth of up to 3.2 gb/second. the fsb uses advanced gunning transceiver logic (agtl+) signalling technology, a variant of (g tl+) signaling technology with low power enhancements. the celeron m processor utilizes socketable micro flip-chip pin grid array (micro- fcpga) and surface mount micro flip-chi p ball grid array (micro-fcbga) package technology. the micro-fcpga package plugs into a 479-hole, surface-mount, zero insertion force (zif) socket, which is referred to as the mpga479m socket. 1.1 terminology 1.2 references material and concepts available in the following documents may be beneficial when reading this document. term definition # a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driv en to a low level. for example, when reset# is low, a reset has been requ ested. conversely, when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but descri bes part of a binary sequence (such as address or data ), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlh l? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). xxxx means that the specification or value is yet to be determined. front side bus (fsb) refers to the interface between the processor and system core logic (also known as the chipset components). document document location 1 intel? celeron? m proces sor specification update http://www.intel.com/ design/mobil e/specupdt/ 300303.htm mobile intel? 915pm/gm/gms and 910gml express chipset datasheet http://www.intel.com/ design/mobile/datashts/ 305264.htm mobile intel? 915pm/gm/gms and 910gml express chipset specification update http://www.intel.com/ design/mobil e/specupdt/ 307167.htm intel? i/o controller hub 6 (ich6) family datasheet http://www.intel.com/ design/chipsets/datashts/ 301473.htm intel? i/o controller hub 6 (ich6) family specification update http://www.intel.com/ design/chipset s/specupdt/ 301474.htm intel? 855pm chipset memory controller hub (mch) datasheet http://www.intel.com/ design/chipsets/datashts/ 252613.htm
datasheet 9 introduction intel? 855pm chipset mch ddr 333/200/266 mhz specification update http://www.intel.com/ design/chipsets/specupdt/ 253488.htm intel? 855gm/gme chipset graphics and memory controller hub (gmch) datasheet http://www.intel.com/ design/chipsets/datashts/ 252615.htm intel? 855gm/gme chipset graphics and memory controller hub (gmch) specification update http://www.intel.com/ design/chipsets/specupdt/ 253572.htm intel? 82801dbm i/o controller hub 4 mobile (ich4-m) datasheet http://www.intel.com/ design/mobile/datashts/ 252337.htm intel? 82801dbm i/o controller hub 4 mobile (ich4-m) datasheet specification update http://www.intel.com/ design/chipsets/specupdt/ 252663.htm ia-32 intel? architecture software developer's manual s http://www.intel.com/ design/pentium4/manuals/ index_new.htm volume 1: basic architecture volume 2a: instruction set reference, a- m volume 2b: instructio n set reference, n-z volume 3a: system programming guide volume 3b: system programming guide document document location 1
introduction 10 datasheet
datasheet 11 low power features 2 low power features 2.1 clock control and low power states the celeron m processor supports the autoha lt power-down, stop grant, sleep, deep sleep states for optimal power management. see figure 1 for a visual representation of the processor low-power states. 2.1.1 normal state this is the normal operating state for the processor. 2.1.2 autohalt power-down state autohalt power-down is a low-power state entered when the processor executes the halt instruction. the processor will transition to the normal state upon the occurrence of smi#,init#, lint[1:0] (nmi, intr), or fsb interrupt message. reset# will cause the processor to immediately initialize itself. the system can generate a stpclk# while the processor is in the autohalt power- down state. when the system deasserts the stpclk# in terrupt, the processor will return execution to the halt state. while in autohalt power-down state, the processor will process bus snoops and interrupts. 2.1.3 stop-grant state when the stpclk# pin is asserted, the stop-g rant state of the processor is entered 20 bus clocks after the response phase of th e processor issued stop-grant acknowledge special bus cycle. figure 1. clock control states snoop occurs stop grant normal sleep halt/ grant snoop auto halt deep sleep stpclk# asserted slp# asserted slp# deasserted stpclk# deasserted snoop serviced hlt instruction snoop serviced snoop occurs dpslp# de-asserted dpslp# asserted stpclk# asserted stpclk# deasserted halt break v0001-04 halt break - a20m#, init#, intr, nmi, preq#, reset#, smi#, or apic interrupt
low power features 12 datasheet since the agtl+ signal pins receive power from the fsb, these pins should not be driven (allowing the level to return to v ccp ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the fsb should be driven to the inactive state. reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the deassertion of the stpclk# signal. when re -entering the stop-grant state from the sleep state, stpclk# should be deassert ed ten or more bus clocks after the deassertion of slp#. a transition to the halt/grant snoop stat e will occur when the processor detects a snoop on the fsb (see section 2.1.4 ). a transition to the sleep state (see section 2.1.5 ) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init# and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event will be recogniz ed upon return to the normal state. while in stop-grant state, the processor will process snoops on the fsb, and it will latch interrupts delivered on the fsb. the pbe# signal can be driven when the proc essor is in stop-grant state. pbe# will be asserted if there is any pending interrupt latched within the processor. pending interrupts that are blocked by the eflags.if bit being clear will still cause assertion of pbe#. assertion of pbe# indicates to system lo gic that it should return the processor to the normal state. 2.1.4 halt/grant snoop state the processor will respond to snoop or interrupt transactions on the fsb while in stop- grant state or in autohalt power-down state. during a snoop or interrupt transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the fsb has been serviced (whether by the processor or another agent on the fsb) or the interrupt has been latched. after the snoop is serviced or the interrupt is latched, the processor will return to the stop-grant state or autohalt power-down state, as appropriate. 2.1.5 sleep state a low power state in which the processor ma intains its context, maintains the phase- locked loop (pll), and has stopped all internal clocks. the sleep state can be entered only from stop-grant state. once in the st op-grant state, the processor will enter the sleep state upon the assertion of the slp# signal. the slp# pin should only be asserted when the processor is in the stop grant state. slp# assertions while the processor is not in the stop-grant state is out of specification and may result in unapproved operation. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapabl e of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp#, dpslp# or reset#) are allowed on the fsb while the processor is in sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unp redictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin sp ecification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor
datasheet 13 low power features is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering an even lower power state, the deep sleep state by asserting the dpslp# pin. (see section 2.1.6 .) while the processor is in the sleep state, the slp# pin must be deasserted if another asynchronous fsb event needs to occur. 2.1.6 deep sleep state deep sleep state is a very low power state the processor can enter while maintaining context. deep sleep state is entered by a sserting the dpslp# pi n while in the sleep state. bclk may be stopped during the deep sleep state for additional platform level power savings. bclk stop/restart timings on 855pm chipset family based platforms with compatible clock generator chips are as follows: ? deep sleep entry - dpslp# and cpu_stp# are asserted simultaneously. the clock chip will stop/tristate bclk within two bclks +/- a few nanoseconds. ? deep sleep exit - dpslp# and cpu_stp# are deasserted simultaneously. the clock chip will drive bclk to differential dc leve ls within 2-3 ns and starts toggling bclk 2-6 bclk periods later. to re-enter the sleep state, the dpslp# pin must be deasserted. bclk can be restarted after dpslp# deassertion as described above. a period of 30 microseconds (to allow for pll stabilization) must occur before the proce ssor can be considered to be in the sleep state. once in the sleep state, the slp# pin must be deasserted to re-enter the stop- grant state. while in deep sleep state, the processo r is incapable of responding to snoop transactions or latching interrupt signals. no transitions of signals are allowed on the fsb while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. when the processor is in deep sleep state, it will not respond to interrupts or snoop transactions. 2.2 fsb low power enhancements the celeron m processor incorporates the fsb low power enhancements: ? dynamic fsb power down ? bpri# control for address and control input buffers ? dynamic on die termination disabling ? low vccp (i/o termination voltage) the celeron m processor incorporates the dpwr# signal that controls the data bus input buffers on the processor. the dpwr# signal disables the buffers when not used and activates them only when data bus acti vity occurs, resulting in significant power savings with no performance impact. bpri# control also allows the processor address and control input buffers to be turned off wh en the bpri# signal is inactive. the on-die termination on the processor fsb buffers is disabled when the signals are driven low, resulting in additional power savings. the lo w i/o termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low i/o switching power at all times.
low power features 14 datasheet 2.3 processor power status indicator (psi#) signal the celeron m processor incorporates the ps i# signal that is asserted when the processor is in a low power (deep sleep) state. this signal is asserted upon deep sleep entry and deasserted upon exit. psi# can be used to improve the light load efficiency of the voltage regulator, resulting in platfo rm power savings and extended battery life.
datasheet 15 electrical specifications 3 electrical specifications 3.1 power and ground pins for clean, on-chip power distribution, the celeron m processor has a large number of v cc (power) and v ss (ground) inputs. all power pins must be connected to v cc power planes while all v ss pins must be connected to system ground planes. use of multiple power and ground planes is recommended to reduce i*r drop. please refer to the platform design guides for more details. the processor v cc pins must be supplied the voltage determined by the vid (voltage id) pins. 3.1.1 fsb clock (bclk[1:0] ) and processor clocking bclk[1:0] directly controls the fsb interface speed as well as the core frequency of the processor. as in previous generation processors, the celeron m processor core frequency is a multiple of the bclk[1:0] frequency. the celeron m processor uses a differential clocking implementation. 3.2 voltage identification and power sequencing the celeron m processor uses six voltage identification pins, vid[5:0], to support automatic selection of power supply voltages. the vid pins for celeron m processor are cmos outputs driven by the processor vid circuitry. ta b l e 1 specifies the voltage level corresponding to the state of vid[5:0].
electrical specifications 16 datasheet table 1. voltage identification definition vid v cc v vid v cc v 543 2 1 0 54 32 1 0 000 0 0 01.7081000 0 01.196 000 0 0 11.6921000 0 11.180 000 0 1 01.6761000 1 01.164 000 0 1 11.6601000 1 11.148 000 1 0 01.6441001 0 01.132 000 1 0 11.6281001 0 11.116 000 1 1 01.6121001 1 01.100 000 1 1 11.5961001 1 11.084 001 0 0 01.5801010 0 01.068 001 0 0 11.5641010 0 11.052 001 0 1 01.5481010 1 01.036 001 0 1 11.5321010 1 11.020 001 1 0 01.5161011 0 01.004 001 1 0 11.5001011 0 10.988 001 1 1 01.4841011 1 00.972 001 1 1 11.4681011 1 10.956 010 0 0 01.4521100 0 00.940 010 0 0 11.4361100 0 10.924 010 0 1 01.4201100 1 00.908 010 0 1 11.4041100 1 10.892 010 1 0 01.3881101 0 00.876 010 1 0 11.3721101 0 10.860 010 1 1 01.3561101 1 00.844 010 1 1 11.3401101 1 10.828 011 0 0 01.3241110 0 00.812 011 0 0 11.3081110 0 10.796 011 0 1 01.2921110 1 00.780 011 0 1 11.2761110 1 10.764 011 1 0 01.2601111 0 00.748 011 1 0 11.2441111 0 10.732 011 1 1 01.2281111 1 00.716 011 1 1 11.2121111 1 10.700
datasheet 17 electrical specifications 3.3 catastrophic thermal protection the celeron m processor supports the thermtrip# signal for catastrophic thermal protection. an external thermal sensor should also be used to protect the processor and the system against excessive temper atures. even with the activation of thermtrip#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. if the external thermal sensor detects a catastrophic processor temperature of 125c (maximum), or if the thermtrip# signal is asserted, the v cc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. 3.4 signal terminations and unused pins all rsvd (reserved) pins must remain unc onnected. connection of these pins to v cc , v ss , or to any other signal (including each other) can result in component malfunction or incompatibility with future celeron m processors. see section 4.2 for a pin listing of the processor and the location of all rsvd pins. for reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. unused active low agtl+ inputs may be left as no connects if agtl+ termination is provided on the proc essor silicon. unused active high inputs should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected. the test1 and test2 pins must have a stuffing option connection to v ss separately via 1-k , pull-down resistors. 3.5 fsb frequency select signals (bsel[1:0]) the bsel[1:0] signals are used to select the frequency of the processor input clock (bclk[1:0]). these signals should be connect ed to the clock chip and intel 915pm/gm/ gms and 910gml express chipset on the platform. these signals must be left unconnected on platforms designed with the celeron m processor and the intel 852/ 855 chipset families. 3.6 fsb signal groups in order to simplify the following discussion, the fsb signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers, which use gtlref as a reference level. in this docume nt, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, ?agtl+ output? refers to the agtl+ output grou p as well as the agtl+ i/o group when driving. with the implementation of a source synchr onous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals which are dependant upon the rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the risi ng edge of bclk0. as ychronous signals are still present (a20m#, ignne#, etc.) and can become active at any time during the clock cycle. ta b l e 2 identifies which signals are common clock, source synchronous, and asynchronous.
electrical specifications 18 datasheet notes: 1. bpm[2:0}# and prdy# are ag tl+ output only signals. 2. in processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. in system s with the debug port im plemented on the system board, these signals are no connects. table 2. fsb pin groups signal group type signals agtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, dpwr#, preq#, reset#, rs[2:0]#, trdy# agtl+ common clock i/o synchronous to bclk[1:0] ads#, bnr#, bpm[3:0]#, br0#, dbsy#, drdy#, hit#, hitm#, lock#, prdy# agtl+ source synchronous i/o synchronous to assoc. strobe agtl+ strobes synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# cmos input asynchronous a20m#, dpslp#, ignne# , init#, lint0/intr, lint1/nmi, pwrgood, smi#, slp#, stpclk# open drain output asynchronous ferr#, ierr#, prochot#, thermtrip# cmos output asynchronous psi#, vid[5:0], bsel[1:0] cmos input synchronous to tck tck, tdi, tms, trst# open drain output synchronous to tck tdo fsb clock clock bclk[1:0], itp_clk[1:0] 2 power/other comp[3:0], dbr# 2 , gtlref, rsvd, test2, test1, thermda, thermdc, v cc , v cca [3:0], v ccp, v ccq [1:0], v cc_sense , v ss , v ss_sense signals associated strobe req[4:0]#, a[16:3]# adstb[0]# a[31:17]# adstb[1]# d[15:0]#, dinv0# dstbp0#, dstbn0# d[31:16]#, dinv1# dstbp1#, dstbn1# d[47:32]#, dinv2# dstbp2#, dstbn2# d[63:48]#, dinv3# dstbp3#, dstbn3#
datasheet 19 electrical specifications 3.7 cmos signals cmos input signals are shown in ta b l e 2 . legacy output ferr#, ierr# and other non- agtl+ signals (thermtrip# and prochot#) utilize open drain output buffers. these signals do not have setup or hold time specif ications in relation to bclk[1:0]. however, all of the cmos signals are required to be as serted for at least three bclks in order for the processor to recognize them. see section 3.9 for the cmos signal group dc specifications. 3.8 maximum ratings ta b l e 3 lists the processor?s maximum environmental stress ratings. the processor should not receive a clock while subjected to these conditions. functional operating parameters are listed in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from electro static discharge (esd), one should always take precautions to avoid high static voltages or electric fields. notes: 1. this rating applies to any processor pin. 2. contact intel for storage requir ements in excess of one year. 3.9 processor dc specifications the processor dc specificat ions in this section are defined at the processor core (pads) unless noted otherwise . see ta b l e 2 for pin signal definitions and signal pin assignments. most of the signals on the fsb are in the agtl+ signal group. the dc specifications for these signals are listed in ta b l e 9 . dc specifications for the cmos group are listed in ta b l e 1 0 . ta b l e 4 through ta b l e 1 0 list the dc specifications for the celeron m processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. active mode load line specif ications apply in all states except in the deep sleep state. v cc,boot is the default voltage driven by the voltage regulator at power up in order to set the vid values. un less specified otherwise, all specifications for the celeron m processor are at tjunction = 100 c. care should be taken to read all notes associated with each parameter. table 3. processor dc ab solute maximum ratings symbol parameter min max unit notes t storage processor storage temperature -40 85 c 2 v cc any processor supply voltage with respect to v ss -0.3 1.6 v 1 v inagtl+ agtl+ buffer dc input voltage with respect to v ss -0.1 1.6 v 1, 2 v inasynch_cmos cmos buffer dc input voltage with respect to v ss -0.1 1.6 v 1, 2
electrical specifications 20 datasheet table 4. voltage and current sp ecifications (sheet 1 of 2) symbol parameter min typ max unit notes v cc1 intel? celeron? m processor 360, 350 core v cc 1.260 v 1,2,9 v cc2 celeron m processor 390, 380, 370, 360j, 350j core v cc 1.004 1.292 v 2,9,11 v cc3 celeron m processor ultra low voltage 383, 373 core v cc 0.876 0.956 v 2,9,11, 12 v cculv celeron m processor ultra low voltage 353 core v cc 0.940 v 1,2,9 v cc,boot default v cc voltage for initial power-up 1.14 1.20 1.26 v 2 v ccp agtl+ termination voltage 0.997 1.05 1.102 v 2 v cca pll supply voltages 1.71 1.425 1.8 1.5 1.89 1.575 v2,10 i ccdes i cc for celeron m processor recommended design target 25 a 5 i cc i cc for celeron m processor 390, 380, 370, 360j, 350j & v cc2 21.0 a 3,9,11 i cc for celeron m processor 360, 350 &1.260 v 21.0 a 3,9 i cculv i cc for celeron m processor ultra low voltage 383, 373 & v cc3 7.0 a 3,9,11, 12 i cc for celeron m processor ultra low voltage 353 & 0.940 v 7.0 a 3,9 i ah, i sgnt i cc auto-halt & stop-grant for celeron m processor 390, 380, 370, 360j, 350j & v cc2 16.4 a 4,9,11 i cc auto-halt & stop-grant for celeron m processor 360, 350 & 1.260 v 16.4 a 4,9 i ahulv, i sgntulv i cc auto-halt & stop-grant for celeron m processor ultra low voltage 383, 373 & v cc3 3.4 a 4,9,11, 12 i cc auto-halt & stop-grant for celeron m processor ultra low voltage 353 & 0.940 v 3.4 a 4,9 i slp i cc sleep for celeron m processor 390, 380, 370, 360j, 350j & v cc2 16.1 a 4,9,11 i cc sleep for celeron m processor 360, 350 & 1.260 v 16.1 a 4,9 i slpulv i cc sleep for celeron m processor ultra low voltage 383, 373 & v cc3 3.3 a 4,9,11, 12 i cc sleep for celeron m processor ultra low voltage 353 & 0.940 v 3.3 a 4,9 i dslp i cc deep sleep for celeron m processor 390, 380, 370, 360j, 350j & v cc2 15.5 a 4,9,11 i cc deep sleep for celeron m processor 360, 350 & 1.260 v 15.5 a 4,9
datasheet 21 electrical specifications notes: 1. the typical values shown are the vid encoded voltag es. static and ripple tole rances (for minimum and maximum voltages) are defined in the loadline tables i.e., ta b l e 5 through ta b l e 7 . 2. the voltage specifications are assumed to be measured at a via on the motherboar d?s opposite side of the processor?s socket (or bga) ball with a 100-mhz bandwidth oscilloscope , 1.5-pf maximum probe capacitance, and 1-m minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 3. specified at v cc,static (nominal) under maximum signal loading conditions. 4. specified at the vid voltage. 5. the i ccdes (max) specification comprehends future proc essor hfm frequencies. platforms should be designed to this specification. 6. based on simulations and averaged over the durati on of any change in curre nt. specified by design/ characterization at nominal v cc . not 100% tested. 7. measured at the bulk capa citors on the motherboard. 8. adherence to loadline specificatio n for the celeron m processor is requ ired to ensure reliable processor operation. 9. intel processor numbers are not a measure of perf ormance. processor number s differentiate features within each processor fa mily, not across different processor families. se e www.intel.com/products/ processor_number for details. 10. the celeron m processor will support v cca supply voltage of either 1.8 v 5% or 1.5 v 5%. either one of these voltages can be used on the platform. 11. these are vid values. individual processor vid values may be calibrated during manufacturing such that two devices at the same speed may have different vi d settings. actual voltage supplied to the processor should be as specified in the load lines in figure 5 and figure 6 . adherence to load line specifications is required to ensure reli able processor operation. 12. for 350j and 360j, cpu signature = 06d8h. i dslpulv i cc deep sleep for celeron m processor ultra low voltage 383, 373 & v cc3 3.0 a 4,9,11, 12 i cc deep sleep for celeron m processor ultra low voltage 353 & 0.940 v 3.0 a 4,9 di cc/dt v cc power supply current slew rate 0.5 a/ns 6, 7 i cca i cc for v cca supply 120 ma i ccp i cc for v ccp supply 2.5 a table 4. voltage and current sp ecifications (sheet 2 of 2) symbol parameter min typ max unit notes
electrical specifications 22 datasheet table 5. voltage tolerances for the ce leron m processor (deep sleep state) mode vid = 1.260 v, offset = 1.2% i cc , a v cc , v static ripple min max min max deep sleep 0.0 1.245 1.226 1.264 1.216 1.274 1.0 1.242 1.223 1.261 1.213 1.271 2.1 1.239 1.220 1.258 1.210 1.268 3.1 1.236 1.217 1.254 1.207 1.264 4.1 1.232 1.214 1.251 1.204 1.261 5.2 1.229 1.210 1.248 1.200 1.258 6.2 1.226 1.207 1.245 1.197 1.255 7.2 1.223 1.204 1.242 1.194 1.252 8.3 1.220 1.201 1.239 1.191 1.249 9.3 1.217 1.198 1.236 1.188 1.246 10.3 1.214 1.195 1.233 1.185 1.243 11.4 1.211 1.192 1.230 1.182 1.240 12.4 1.208 1.189 1.227 1.179 1.237 13.4 1.205 1.186 1.223 1.176 1.233 14.5 1.201 1.183 1.220 1.173 1.230 15.5 1.198 1.179 1.217 1.169 1.227 figure 2. illustration of deep sleep state v cc static and ripple tolerances for the celeron m processor (d eep sleep state): vid=1.260 v vid = 1.260: deep sleep 1.245 1.160 1.180 1.200 1.220 1.240 1.260 1.280 0.0 2.0 4.0 6.0 8.0 10.0 12.0 static static min static max ripple min ripple max
datasheet 23 electrical specifications table 6. voltage tolerances for the celeron m processor ulv (active state) mode vid = 0.940 v, offset=0% i cc , a v cc , v static ripple minmaxminmax active 0 0.940 0.926 0.954 0.916 0.964 0.3 0.939 0.925 0.953 0.915 0.963 0.5 0.938 0.924 0.953 0.914 0.963 0.8 0.938 0.924 0.952 0.914 0.962 1.0 0.937 0.923 0.951 0.913 0.961 1.3 0.936 0.922 0.950 0.912 0.960 1.6 0.935 0.921 0.949 0.911 0.959 1.8 0.935 0.920 0.949 0.910 0.959 2.1 0.934 0.920 0.948 0.910 0.958 2.3 0.933 0.919 0.947 0.909 0.957 2.6 0.932 0.918 0.946 0.908 0.956 2.9 0.931 0.917 0.946 0.907 0.956 3.1 0.931 0.917 0.945 0.907 0.955 3.4 0.930 0.916 0.944 0.906 0.954 3.6 0.929 0.915 0.943 0.905 0.953 3.9 0.928 0.914 0.942 0.904 0.952 4.1 0.928 0.913 0.942 0.903 0.952 4.4 0.927 0.913 0.941 0.903 0.951 4.7 0.926 0.912 0.940 0.902 0.950 4.9 0.925 0.911 0.939 0.901 0.949 5.2 0.924 0.910 0.939 0.900 0.949 5.4 0.924 0.910 0.938 0.900 0.948 5.7 0.923 0.909 0.937 0.899 0.947 6.0 0.922 0.908 0.936 0.898 0.946 6.2 0.921 0.907 0.935 0.897 0.945 6.5 0.921 0.906 0.935 0.896 0.945 6.7 0.920 0.906 0.934 0.896 0.944 7.0 0.919 0.905 0.933 0.895 0.943
electrical specifications 24 datasheet figure 3. illustration of active state v cc static and ripple tolerances for the celeron m processor ulv: vid=0.940 v vid = 0.940: active 0.940 0.890 0.900 0.910 0.920 0.930 0.940 0.950 0.960 0.970 0123456 icc, a vcc, v static static min static max ripple min ripple max table 7. voltage tolerances for the celeron m processor ulv (deep sleep state) mode vid = 0.940 v, offset=0% i cc , a v cc , v static ripple min max min max active 0 0.929 0.915 0.943 0.905 0.953 0.2 0.928 0.914 0.942 0.904 0.952 0.4 0.928 0.913 0.942 0.903 0.952 0.6 0.927 0.913 0.941 0.903 0.951 0.8 0.926 0.912 0.940 0.902 0.950 1.0 0.926 0.912 0.940 0.902 0.950 1.2 0.925 0.911 0.939 0.901 0.949 1.4 0.925 0.910 0.939 0.900 0.949 1.6 0.924 0.910 0.938 0.900 0.948 1.8 0.923 0.909 0.937 0.899 0.947 2.0 0.923 0.909 0.937 0.899 0.947 2.2 0.922 0.908 0.936 0.898 0.946 2.4 0.922 0.907 0.936 0.897 0.946 2.6 0.921 0.907 0.935 0.897 0.945 2.8 0.920 0.906 0.934 0.896 0.944 3.0 0.920 0.906 0.934 0.896 0.944
datasheet 25 electrical specifications figure 4. illustration of deep sleep state v cc static and ripple tolerances for the celeron m processor ulv: vid=0.940 v figure 5. active v cc and i cc loadline for the celeron m processor: standard voltage and ultra low voltage vid = 0.940v: deep sleep 0.929 0.890 0.900 0.910 0.920 0.930 0.940 0.950 0.960 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 icc, a vcc, v static static min static max ripple min ripple max i cc max v cc [v] slope= -3.0 mv/a +/-1.5% from nominal =vr error 10mv= ripple i cc [a] 0 v cc, dc max v cc max v cc nom v cc, dc min v cc min
electrical specifications 26 datasheet notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. crossing voltage is defined as abso lute voltage where rising edge of bc lk0 is equal to the falling edge of bclk1. 3. threshold region is define d as a region entered about the crossing voltage in which the differential receiver switches. it includes input threshold hysteresis. 4. for vin between 0 v and v ih . 5. cpad includes die capacitance only. no package parasitics are included. 6. v cross is defined as the total variation of all crossing voltages as defined in note 2. figure 6. deep sleep v cc and i cc loadline for celeron m processors: standard voltage and ultra low voltage table 8. fsb differential bclk specifications symbol parameter min typ max unit notes 1 v ih input high voltage 0.660 0.710 0.850 v v il input low voltage 0 v v cross crossing voltage 0.250.350.55v2 v cross range of crossing points n/a n/a 0.140 v 6 v th threshold region v cross - 0.100 v cross + 0.100 v 3 i li input leakage current 100 a 4 cpad pad capacitance 1.8 2.3 2.75 pf 5 i cc max v cc [v] slope= -3.0 mv/a vcc nom - 1.2% +/-1.5% from nominal =vr error 10mv= ripple i cc [a] 0 deep sleep
datasheet 27 electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. v il is defined as the maximum voltage le vel at a receiving agent that will be interpreted as a logical low value. 3. v ih is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. v ih and v oh may experience excursions above v ccp . however, input signal drivers must comply with the signal quality specifications in chapter 3 . 5. this is the pull-down driver resi stance. refer to processor i/o buffe r models for i/v characteristics. measured at 0.31*v ccp . r on (min) = 0.38*r tt , r on (typ) = 0.45*r tt , r on (max) = 0.52*r tt . 6. gtlref should be generated from v ccp with a 1% tolerance re sistor divider. the v ccp referred to in these specifications is the instantaneous v ccp . 7. r tt is the on-die termination resistance measured at v ol of the agtl+ output driver. measured at 0.31*v ccp . r tt is connected to v ccp on die. refer to processor i/o bu ffer models for i/v characteristics. 8. specified with on die r tt and r on are turned off. 9. cpad includes die capacitance only. no package parasitics are included. notes: 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. the v ccp referred to in these specificat ions refers to instantaneous v ccp . 3. measured at 0.1*v ccp . 4. measured at 0.9*v ccp . 5. for vin between 0 v and v ccp . measured when the driver is tristated. 6. cpad includes die capacitance only. no package parasitics are included. table 9. agtl+ signal group dc specifications symbol parameter min typ max unit notes 1 v ccp i/o voltage 0.997 1.05 1.102 v gtlref reference voltage 2/3 v ccp - 2% 2/3 v ccp 2/3 v ccp + 2% v 6 v ih input high volt age gtlref + 0.1 v ccp + 0.1 v 3,6 v il input low voltage -0.1 gtlref - 0.1 v 2,4 v oh output high voltage v ccp 6 r tt termination resistance 47 55 63 7 r on buffer on resistance 17.7 24.7 32.9 5 i li input leakage current 100 a 8 cpad pad capacitance 1.8 2.3 2.75 pf 9 table 10. cmos signal group dc specifications symbol parameter min typ max unit notes 1 v ccp i/o voltage 0.997 1.05 1.102 v v ih input high voltage 0.7*v ccp v ccp +0.1 v 2 v il input low voltage cmos -0.1 0.3*v ccp v2, 3 v oh output high voltage 0.9*v ccp v ccp v ccp +0.1 v 2 v ol output low voltage -0.1 0 0.1*v ccp v2 i oh output high current 1.49 4.08 ma 5 i ol output low current 1.49 4.08 ma 4 i li input leakage current 100 a 6 cpad pad capacitance 1.0 2.3 3.0 pf
electrical specifications 28 datasheet notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. measured at 0.2 v. 3. v oh is determined by value of the external pull-up resistor to v ccp . 4. for vin between 0 v and v oh . 5. cpad includes die capacitance only. no package parasitics are included. table 11. open drain signal group dc specifications symbol parameter min typ max unit notes 1 v oh output high voltage v ccp v3 v ol output low voltage 0 0.20 v i ol output low current 16 50 ma 2 i lo output leakage current 200 a 4 cpad pad capacitance 1.7 2.3 3.0 pf 5
datasheet 29 package mechanical specifications and pin information 4 package mechanical specifications and pin information the celeron m processor will be available in 478-pin, micro-fcpga and 479-ball, micro- fcbga packages. different views of th e micro-fcpga package are shown in figure 7 through figure 9 . package dimensions are shown in figure 7 . different views of the micro-fcbga package are shown in figure 7 through figure 9 . package dimensions are shown in ta b l e 8 . the micro-fcbga package may have capacitors placed in the area surrounding the die. because the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. doing so may short the capacitors, and possibly damage the device or render it inactive. th e use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. note: all dimensions in millimeters. values shown for reference only. refer to ta b l e 1 2 for details. figure 7. micro-fcpga package to p and bottom isometric views top view bottom view label package keepout die capacitor area
package mechanical specifications and pin information 30 datasheet note: die is centered on the package. all dimensions in millimeters. values shown for reference only. refer to ta b l e 1 2 for details. figure 8. micro-fcpga package - top and side views 35 (e) 35 (d) pin a1 corner e1 d1 a 1.25 max (a3) ? 0.32 (b) 478 places 2.03 0.08 (a1) a2 substrate keepout zone do not contact package in s id e th is l in e 7 (k1) 8 places 5 (k) 4 places 0.286 35 (e) 35 (d) pin a1 corner e1 d1 a 1.25 max (a3) ? 0.32 (b) 478 places 2.03 0.08 (a1) a2 substrate keepout zone do not contact package in s id e th is l in e 7 (k1) 8 places 5 (k) 4 places 0.286 0.286
datasheet 31 package mechanical specifications and pin information note: all dimensions in millimeters. values shown for reference only. refer to ta b l e 1 2 for details. figure 9. micro-fcpga package - bottom view 1 2 3 4 6 8 10 12 14 16 18 20 22 24 26 5 7 9 11 13 15 17 19 21 23 25 a b c e d f g h j k l m n p r t u v w y aa ab ac ad ae af 25x 1.27 (e) 25x 1.27 (e) 14 (k3) 14 (k3)
package mechanical specifications and pin information 32 datasheet notes: 1. overall height with socket is based on desi gn dimensions of the mi cro-fcpga package with no thermal solution attached. values are base d on design specificat ions and tolerances. this dimension is subject to change based on socket design, oem motherboard design or oem smt process. table 12. micro-fcpga package dimensions symbol parameter min max unit a overall height, top of the die to package seating plane 1.88 2.02 mm ? overall height, top of die to pcb surface, including socket (refer to note 1) 4.74 5.16 mm a1 pin length 1.95 2.11 mm a2 die height 0.820 mm a3 pin-side capacitor height ? 1.25 mm b pin diameter 0.28 0.36 mm d package substrate length 34.9 35.1 mm e package substrat e width 34.9 35.1 mm d1 die length 12.54 mm e1 die width 6.99 mm epin pitch 1.27 mm k package edge keep-out 5 mm k1 package corner keep-out 7 mm k3 pin-side capacitor boundary 14 mm n pin count 478 each pdie allowable pressure on the die for thermal solution - 689 kpa wpackage weight 4.5 g package surface flatness 0.286 mm
datasheet 33 package mechanical specifications and pin information figure 10. micro-fcbga package top and bottom isometric views top view bottom view label die package keepout capacitor area
package mechanical specifications and pin information 34 datasheet note: die is centered on the package. all dimensions in millimeters. values shown for reference only. refer to ta b l e 1 3 for details. figure 11. micro-fcbga package top and side views 35 (e) 35 (d) pin a1 corner e1 d1 a ? 0.78 (b) 479 places k2 substrate keepout zone do not contact package inside this line 7 (k1) 8 places 5 (k) 4 places a2 0.20
datasheet 35 package mechanical specifications and pin information notes: 1. overall height as delivered. values are based on design spec ifications and tolerances. this dimension is subject to chan ge based on oem motherboard design or oem smt process table 13. micro-fcpga package dimensions symbol parameter min max unit a overall height, as delivered (refer to note 1) 2.60 2.85 mm a2 die height 0.82 mm b ball diameter 0.78 mm d package substrate length 34.9 35.1 mm e package substrate width 34.9 35.1 mm d1 die length 12.54 mm e1 die width 6.99 mm eball pitch 1.27 mm k package edge keep-out 5 mm k1 package corner keep-out 7 mm k2 die-side capacitor height ? 0.7 mm s package edge to first ball center 1.625 mm n ball count 479 each ? solder ball coplanarity 0.2 mm pdie allowable pressure on the die for thermal solution ? 689 kpa wpackage weight 4.5 g
package mechanical specifications and pin information 36 datasheet note: all dimensions in millimeters. values shown for reference only. refer to ta b l e 1 3 for details. figure 12. micro-fcbga package bottom view 1 2 3 4 6 8 10 12 14 16 18 20 22 24 26 5 7 9 11 13 15 17 19 21 23 25 a b c e d f g h j k l m n p r t u v w y aa ab ac ad ae af 25x 1.27 (e) 25x 1.27 (e) 1.625 (s) 4 places 1.625 (s) 4 places
datasheet 37 package mechanical specifications and pin information 4.1 processor pinout and pin list figure 13 shows the top view pinout of the celeron m processor. the pin list arranged in two different formats is shown in the following pages.
package mechanical specifications and pin information 38 datasheet figure 13. the coordinates of the processor pins as viewed from the top of the package 1234567891011121314151617181920212223242526 ignne# ierr# vss slp# dbr# vss bpm[2]# prdy# vss tdo tck vss itp_clk [1] itp_clk [0] vss ther mdc d[0]# vss d[6]# d[2]# vss d[4]# d[1]# vss vss smi# init# vss dpslp# bpm [1]# vss preq# reset # vss trst# bclk1 bclk0 vss proc hot # ther mda vss d[7]# d[3]# vss d[13]# d[9]# vss d[5]# vss a20m# rsvd vss test1 stp clk# vss bpm [0]# bpm [3]# vss tms tdi vss bsel[1] vss bsel[0] therm trip# vss dpwr# d[8]# vss dstbp [0]# dstbn [0]# vss d[15]# d[12]# lint0 vss ferr# lint1 vss vcc vss vcc vss vccp vss vccp vss vccp vss vccp vss vcc vss vcc vss vcc vss d[10]# dinv [0]# vss psi# vid[0] pwr good vcc vss vcc vss vcc vss vccp vss vccp vss vccp vss vcc vss vcc vss vcc vss d[14]# d[11]# vss rsvd vss vid[1] vid[2] vss vss vcc vss vcc vss vccp vss vccp vss vccp vss vccp vss vcc vss vcc vss vcc test2 vss d[21]# vcca[0] rsvd vss vid[3] vid[4] vcc vss vcc vss vss d[22]# d[17]# vss rs[0]# drdy# vss vid[5] vss vcc vss vcc d[16]# d[20]# vss d[29]# vss lock# bpri# vss vcc vss vcc vss d[23]# vss d[25]# dinv [1]# rs[1]# vss hit# hit m# vss vccp vss vcc vss dstbn [1]# d[31]# vss bnr# rs[2]# vss defer# vccp vss vccp vss d[18]# dstbp [1]# vss d[26]# dbsy# trdy# vss vss vccp vss vccp d[24]# vss d[28]# d[19]# vcca[2] ads# vss br0# vccp vss vccp vss vss d[27]# d[30]# vss req [3]# vss req [1]# a[3]# vss vccp vss vccp vccq[0] vss comp [0] comp [1] vss req [0]# a[6]# vss vccp vss vccp vss d[39]# d[37]# vss d[38]# req [4]# req [2]# vss a[9]# vss vccp vss vccp vss dinv [2]# d[34]# vss a[13]# vss adst b [0]# a[4]# vcc vss vccp vss d[35]# vss d[43]# d[41]# vss a[7]# a[5]# vss vss vcc vss vcc d[36]# d[42]# vss d[44]# a[8]# a[10]# vss vccq[1] vcc vss vcc vss vss dstbp [2]# dstbn [2]# vss a[12]# vss a[15]# vss vcc vss vcc d[45]# vss d[47]# d[32]# vss a[16]# a[14]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d[40]# d[33]# vss d[46]# comp [3] comp [2] vss a[24]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d[50]# d[48]# vss rsvd vss a[20]# a[18]# vss a[25]# a[19]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc d[51]# vss d[52]# d[49]# vss d[53]# vcca[3] vss a[23]# a[21]# vss a[26]# a[28]# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss dinv [3]# d[60]# vss d[54]# d[57]# vss gtlref a[30]# a[27]# vss a[22]# adst b [1]# vss vcc sense vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d[59]# d[55]# vss dstbn [3]# dstbp [3]# vss a[31]# a[31]# vss a[29]# a[17]# vss vss sense rsvd vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d[58]# vss d[62]# d[56]# vss d[61]# d[63]# a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vss a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 vss vcc other vss a[11]# vss top view vcca[1] pin b2 is depopulated on the micro-fcpga package rsvd
datasheet 39 package mechanical specifications and pin information table 14. pin listing by pin name pin name pin # signal buffer type direction a[3]# p4 source synch input/ output a[4]# u4 source synch input/ output a[5]# v3 source synch input/ output a[6]# r3 source synch input/ output a[7]# v2 source synch input/ output a[8]# w1 source synch input/ output a[9]# t4 source synch input/ output a[10]# w2 source synch input/ output a[11]# y4 source synch input/ output a[12]# y1 source synch input/ output a[13]# u1 source synch input/ output a[14]# aa3 source synch input/ output a[15]# y3 source synch input/ output a[16]# aa2 source synch input/ output a[17]# af4 source synch input/ output a[18]# ac4 source synch input/ output a[19]# ac7 source synch input/ output a[20]# ac3 source synch input/ output a[21]# ad3 source synch input/ output a[22]# ae4 source synch input/ output a[23]# ad2 source synch input/ output a[24]# ab4 source synch input/ output a[25]# ac6 source synch input/ output a[26]# ad5 source synch input/ output a[27]# ae2 source synch input/ output a[28]# ad6 source synch input/ output a[29]# af3 source synch input/ output a[30]# ae1 source synch input/ output a[31]# af1 source synch input/ output a20m# c2 cmos input ads# n2 common clock input/ output adstb[0]# u3 source synch input/ output adstb[1]# ae5 source synch input/ output bclk[0] b15 bus clock input bclk[1] b14 bus clock input bnr# l1 common clock input/ output bpm[0]# c8 common clock output bpm[1]# b8 common clock output bpm[2]# a9 common clock output bpm[3]# c9 common clock input/ output bpri# j3 common clock input br0# n4 common clock input/ output bsel[1] c14 cmos output bsel[0] c16 cmos output comp[0] p25 power/other input/ output table 14. pin listing by pin name pin name pin # signal buffer type direction
package mechanical specifications and pin information 40 datasheet comp[1] p26 power/other input/ output comp[2] ab2 power/other input/ output comp[3] ab1 power/other input/ output d[0]# a19 source synch input/ output d[1]# a25 source synch input/ output d[2]# a22 source synch input/ output d[3]# b21 source synch input/ output d[4]# a24 source synch input/ output d[5]# b26 source synch input/ output d[6]# a21 source synch input/ output d[7]# b20 source synch input/ output d[8]# c20 source synch input/ output d[9]# b24 source synch input/ output d[10]# d24 source synch input/ output d[11]# e24 source synch input/ output d[12]# c26 source synch input/ output d[13]# b23 source synch input/ output d[14]# e23 source synch input/ output d[15]# c25 source synch input/ output d[16]# h23 source synch input/ output d[17]# g25 source synch input/ output d[18]# l23 source synch input/ output table 14. pin listing by pin name pin name pin # signal buffer type direction d[19]# m26 source synch input/ output d[20]# h24 source synch input/ output d[21]# f25 source synch input/ output d[22]# g24 source synch input/ output d[23]# j23 source synch input/ output d[24]# m23 source synch input/ output d[25]# j25 source synch input/ output d[26]# l26 source synch input/ output d[27]# n24 source synch input/ output d[28]# m25 source synch input/ output d[29]# h26 source synch input/ output d[30]# n25 source synch input/ output d[31]# k25 source synch input/ output d[32]# y26 source synch input/ output d[33]# aa24 source synch input/ output d[34]# t25 source synch input/ output d[35]# u23 source synch input/ output d[36]# v23 source synch input/ output d[37]# r24 source synch input/ output d[38]# r26 source synch input/ output d[39]# r23 source synch input/ output d[40]# aa23 source synch input/ output table 14. pin listing by pin name pin name pin # signal buffer type direction
datasheet 41 package mechanical specifications and pin information d[41]# u26 source synch input/ output d[42]# v24 source synch input/ output d[43]# u25 source synch input/ output d[44]# v26 source synch input/ output d[45]# y23 source synch input/ output d[46]# aa26 source synch input/ output d[47]# y25 source synch input/ output d[48]# ab25 source synch input/ output d[49]# ac23 source synch input/ output d[50]# ab24 source synch input/ output d[51]# ac20 source synch input/ output d[52]# ac22 source synch input/ output d[53]# ac25 source synch input/ output d[54]# ad23 source synch input/ output d[55]# ae22 source synch input/ output d[56]# af23 source synch input/ output d[57]# ad24 source synch input/ output d[58]# af20 source synch input/ output d[59]# ae21 source synch input/ output d[60]# ad21 source synch input/ output d[61]# af25 source synch input/ output d[62]# af22 source synch input/ output table 14. pin listing by pin name pin name pin # signal buffer type direction d[63]# af26 source synch input/ output dbr# a7 cmos output dbsy# m2 common clock input/ output defer# l4 common clock input dinv[0]# d25 source synch input/ output dinv[1]# j26 source synch input/ output dinv[2]# t24 source synch input/ output dinv[3]# ad20 source synch input/ output dpslp# b7 cmos input dpwr# c19 common clock input drdy# h2 common clock input/ output dstbn[0]# c23 source synch input/ output dstbn[1]# k24 source synch input/ output dstbn[2]# w25 source synch input/ output dstbn[3]# ae24 source synch input/ output dstbp[0]# c22 source synch input/ output dstbp[1]# l24 source synch input/ output dstbp[2]# w24 source synch input/ output dstbp[3]# ae25 source synch input/ output ferr# d3 open drain output gtlref ad26 power/other input hit# k3 common clock input/ output hitm# k4 common clock input/ output ierr# a4 open drain output table 14. pin listing by pin name pin name pin # signal buffer type direction
package mechanical specifications and pin information 42 datasheet ignne# a3 cmos input init# b5 cmos input itp_clk[0] a16 cmos input itp_clk[1] a15 cmos input lint0 d1 cmos input lint1 d4 cmos input lock# j2 common clock input/ output prdy# a10 common clock output preq# b10 common clock input prochot# b17 open drain output psi# e1 cmos output pwrgood e4 cmos input req[0]# r2 source synch input/ output req[1]# p3 source synch input/ output req[2]# t2 source synch input/ output req[3]# p1 source synch input/ output req[4]# t1 source synch input/ output reset# b11 common clock input rs[0]# h1 common clock input rs[1]# k1 common clock input rs[2]# l2 common clock input rsvd af7 reserved rsvd b2 reserved rsvd c3 reserved rsvd e26 reserved rsvd g1 reserved rsvd ac1 reserved slp# a6 cmos input smi# b4 cmos input table 14. pin listing by pin name pin name pin # signal buffer type direction stpclk# c6 cmos input tck a13 cmos input tdi c12 cmos input tdo a12 open drain output test1 c5 test test2 f23 test thermda b18 power/other thermdc a18 power/other thermtrip# c17 open drain output tms c11 cmos input trdy# m3 common clock input trst# b13 cmos input vcc d6 power/other vcc d8 power/other vcc d18 power/other vcc d20 power/other vcc d22 power/other vcc e5 power/other vcc e7 power/other vcc e9 power/other vcc e17 power/other vcc e19 power/other vcc e21 power/other vcc f6 power/other vcc f8 power/other vcc f18 power/other vcc f20 power/other vcc f22 power/other vcc g5 power/other vcc g21 power/other vcc h6 power/other vcc h22 power/other vcc j5 power/other vcc j21 power/other vcc k22 power/other vcc u5 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction
datasheet 43 package mechanical specifications and pin information vcc v6 power/other vcc v22 power/other vcc w5 power/other vcc w21 power/other vcc y6 power/other vcc y22 power/other vcc aa5 power/other vcc aa7 power/other vcc aa9 power/other vcc aa11 power/other vcc aa13 power/other vcc aa15 power/other vcc aa17 power/other vcc aa19 power/other vcc aa21 power/other vcc ab6 power/other vcc ab8 power/other vcc ab10 power/other vcc ab12 power/other vcc ab14 power/other vcc ab16 power/other vcc ab18 power/other vcc ab20 power/other vcc ab22 power/other vcc ac9 power/other vcc ac11 power/other vcc ac13 power/other vcc ac15 power/other vcc ac17 power/other vcc ac19 power/other vcc ad8 power/other vcc ad10 power/other vcc ad12 power/other vcc ad14 power/other vcc ad16 power/other vcc ad18 power/other vcc ae9 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction vcc ae11 power/other vcc ae13 power/other vcc ae15 power/other vcc ae17 power/other vcc ae19 power/other vcc af8 power/other vcc af10 power/other vcc af12 power/other vcc af14 power/other vcc af16 power/other vcc af18 power/other vcca[0] f26 power/other vcca[1] b1 power/other vcca[2] n1 power/other vcca[3] ac26 power/other vccp d10 power/other vccp d12 power/other vccp d14 power/other vccp d16 power/other vccp e11 power/other vccp e13 power/other vccp e15 power/other vccp f10 power/other vccp f12 power/other vccp f14 power/other vccp f16 power/other vccp k6 power/other vccp l5 power/other vccp l21 power/other vccp m6 power/other vccp m22 power/other vccp n5 power/other vccp n21 power/other vccp p6 power/other vccp p22 power/other vccp r5 power/other vccp r21 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction
package mechanical specifications and pin information 44 datasheet vccp t6 power/other vccp t22 power/other vccp u21 power/other vccq[0] p23 power/other vccq[1] w4 power/other vccsense ae7 power/other output vid[0] e2 cmos output vid[1] f2 cmos output vid[2] f3 cmos output vid[3] g3 cmos output vid[4] g4 cmos output vid[5] h4 cmos output vss a2 power/other vss a5 power/other vss a8 power/other vss a11 power/other vss a14 power/other vss a17 power/other vss a20 power/other vss a23 power/other vss a26 power/other vss b3 power/other vss b6 power/other vss b9 power/other vss b12 power/other vss b16 power/other vss b19 power/other vss b22 power/other vss b25 power/other vss c1 power/other vss c4 power/other vss c7 power/other vss c10 power/other vss c13 power/other vss c15 power/other vss c18 power/other vss c21 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction vss c24 power/other vss d2 power/other vss d5 power/other vss d7 power/other vss d9 power/other vss d11 power/other vss d13 power/other vss d15 power/other vss d17 power/other vss d19 power/other vss d21 power/other vss d23 power/other vss d26 power/other vss e3 power/other vss e6 power/other vss e8 power/other vss e10 power/other vss e12 power/other vss e14 power/other vss e16 power/other vss e18 power/other vss e20 power/other vss e22 power/other vss e25 power/other vss f1 power/other vss f4 power/other vss f5 power/other vss f7 power/other vss f9 power/other vss f11 power/other vss f13 power/other vss f15 power/other vss f17 power/other vss f19 power/other vss f21 power/other vss f24 power/other vss g2 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction
datasheet 45 package mechanical specifications and pin information vss g6 power/other vss g22 power/other vss g23 power/other vss g26 power/other vss h3 power/other vss h5 power/other vss h21 power/other vss h25 power/other vss j1 power/other vss j4 power/other vss j6 power/other vss j22 power/other vss j24 power/other vss k2 power/other vss k5 power/other vss k21 power/other vss k23 power/other vss k26 power/other vss l3 power/other vss l6 power/other vss l22 power/other vss l25 power/other vss m1 power/other vss m4 power/other vss m5 power/other vss m21 power/other vss m24 power/other vss n3 power/other vss n6 power/other vss n22 power/other vss n23 power/other vss n26 power/other vss p2 power/other vss p5 power/other vss p21 power/other vss p24 power/other vss r1 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction vss r4 power/other vss r6 power/other vss r22 power/other vss r25 power/other vss t3 power/other vss t5 power/other vss t21 power/other vss t23 power/other vss t26 power/other vss u2 power/other vss u6 power/other vss u22 power/other vss u24 power/other vss v1 power/other vss v4 power/other vss v5 power/other vss v21 power/other vss v25 power/other vss w3 power/other vss w6 power/other vss w22 power/other vss w23 power/other vss w26 power/other vss y2 power/other vss y5 power/other vss y21 power/other vss y24 power/other vss aa1 power/other vss aa4 power/other vss aa6 power/other vss aa8 power/other vss aa10 power/other vss aa12 power/other vss aa14 power/other vss aa16 power/other vss aa18 power/other vss aa20 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction
package mechanical specifications and pin information 46 datasheet vss aa22 power/other vss aa25 power/other vss ab3 power/other vss ab5 power/other vss ab7 power/other vss ab9 power/other vss ab11 power/other vss ab13 power/other vss ab15 power/other vss ab17 power/other vss ab19 power/other vss ab21 power/other vss ab23 power/other vss ab26 power/other vss ac2 power/other vss ac5 power/other vss ac8 power/other vss ac10 power/other vss ac12 power/other vss ac14 power/other vss ac16 power/other vss ac18 power/other vss ac21 power/other vss ac24 power/other vss ad1 power/other vss ad4 power/other vss ad7 power/other vss ad9 power/other vss ad11 power/other vss ad13 power/other vss ad15 power/other vss ad17 power/other vss ad19 power/other vss ad22 power/other vss ad25 power/other vss ae3 power/other vss ae6 power/other table 14. pin listing by pin name pin name pin # signal buffer type direction vss ae8 power/other vss ae10 power/other vss ae12 power/other vss ae14 power/other vss ae16 power/other vss ae18 power/other vss ae20 power/other vss ae23 power/other vss ae26 power/other vss af2 power/other vss af5 power/other vss af9 power/other vss af11 power/other vss af13 power/other vss af15 power/other vss af17 power/other vss af19 power/other vss af21 power/other vss af24 power/other vsssense af6 power/other output table 15. pin listing by pin number pin # pin name signal buffer type direction a2 vss power/other a3 ignne# cmos input a4 ierr# open drain output a5 vss power/other a6 slp# cmos input a7 dbr# cmos output a8 vss power/other a9 bpm[2]# common clock output a10 prdy# common clock output a11 vss power/other a12 tdo open drain output a13 tck cmos input table 14. pin listing by pin name pin name pin # signal buffer type direction
datasheet 47 package mechanical specifications and pin information a14 vss power/other a15 itp_clk[1] cmos input a16 itp_clk[0] cmos input a17 vss power/other a18 thermdc power/other a19 d[0]# source synch input/ output a20 vss power/other a21 d[6]# source synch input/ output a22 d[2]# source synch input/ output a23 vss power/other a24 d[4]# source synch input/ output a25 d[1]# source synch input/ output a26 vss power/other aa1 vss power/other aa2 a[16]# source synch input/ output aa3 a[14]# source synch input/ output aa4 vss power/other aa5 vcc power/other aa6 vss power/other aa7 vcc power/other aa8 vss power/other aa9 vcc power/other aa10 vss power/other aa11 vcc power/other aa12 vss power/other aa13 vcc power/other aa14 vss power/other aa15 vcc power/other aa16 vss power/other aa17 vcc power/other aa18 vss power/other aa19 vcc power/other table 15. pin listing by pin number pin # pin name signal buffer type direction aa20 vss power/other aa21 vcc power/other aa22 vss power/other aa23 d[40]# source synch input/ output aa24 d[33]# source synch input/ output aa25 vss power/other aa26 d[46]# source synch input/ output ab1 comp[3] power/other input/ output ab2 comp[2] power/other input/ output ab3 vss power/other ab4 a[24]# source synch input/ output ab5 vss power/other ab6 vcc power/other ab7 vss power/other ab8 vcc power/other ab9 vss power/other ab10 vcc power/other ab11 vss power/other ab12 vcc power/other ab13 vss power/other ab14 vcc power/other ab15 vss power/other ab16 vcc power/other ab17 vss power/other ab18 vcc power/other ab19 vss power/other ab20 vcc power/other ab21 vss power/other ab22 vcc power/other ab23 vss power/other ab24 d[50]# source synch input/ output ab25 d[48]# source synch input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction
package mechanical specifications and pin information 48 datasheet ab26 vss power/other ac1 rsvd reserved ac2 vss power/other ac3 a[20]# source synch input/ output ac4 a[18]# source synch input/ output ac5 vss power/other ac6 a[25]# source synch input/ output ac7 a[19]# source synch input/ output ac8 vss power/other ac9 vcc power/other ac10 vss power/other ac11 vcc power/other ac12 vss power/other ac13 vcc power/other ac14 vss power/other ac15 vcc power/other ac16 vss power/other ac17 vcc power/other ac18 vss power/other ac19 vcc power/other ac20 d[51]# source synch input/ output ac21 vss power/other ac22 d[52]# source synch input/ output ac23 d[49]# source synch input/ output ac24 vss power/other ac25 d[53]# source synch input/ output ac26 vcca[3] power/other ad1 vss power/other ad2 a[23]# source synch input/ output ad3 a[21]# source synch input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction ad4 vss power/other ad5 a[26]# source synch input/ output ad6 a[28]# source synch input/ output ad7 vss power/other ad8 vcc power/other ad9 vss power/other ad10 vcc power/other ad11 vss power/other ad12 vcc power/other ad13 vss power/other ad14 vcc power/other ad15 vss power/other ad16 vcc power/other ad17 vss power/other ad18 vcc power/other ad19 vss power/other ad20 dinv[3]# source synch input/ output ad21 d[60]# source synch input/ output ad22 vss power/other ad23 d[54]# source synch input/ output ad24 d[57]# source synch input/ output ad25 vss power/other ad26 gtlref power/other ae1 a[30]# source synch input/ output ae2 a[27]# source synch input/ output ae3 vss power/other ae4 a[22]# source synch input/ output ae5 adstb[1]# source synch input/ output ae6 vss power/other ae7 vccsense power/other output table 15. pin listing by pin number pin # pin name signal buffer type direction
datasheet 49 package mechanical specifications and pin information ae8 vss power/other ae9 vcc power/other ae10 vss power/other ae11 vcc power/other ae12 vss power/other ae13 vcc power/other ae14 vss power/other ae15 vcc power/other ae16 vss power/other ae17 vcc power/other ae18 vss power/other ae19 vcc power/other ae20 vss power/other ae21 d[59]# source synch input/ output ae22 d[55]# source synch input/ output ae23 vss power/other ae24 dstbn[3]# source synch input/ output ae25 dstbp[3]# source synch input/ output ae26 vss power/other af1 a[31]# source synch input/ output af2 vss power/other af3 a[29]# source synch input/ output af4 a[17]# source synch input/ output af5 vss power/other af6 vsssense power/other output af7 rsvd reserved af8 vcc power/other af9 vss power/other af10 vcc power/other af11 vss power/other af12 vcc power/other af13 vss power/other table 15. pin listing by pin number pin # pin name signal buffer type direction af14 vcc power/other af15 vss power/other af16 vcc power/other af17 vss power/other af18 vcc power/other af19 vss power/other af20 d[58]# source synch input/ output af21 vss power/other af22 d[62]# source synch input/ output af23 d[56]# source synch input/ output af24 vss power/other af25 d[61]# source synch input/ output af26 d[63]# source synch input/ output b1 vcca[1] power/other b2 rsvd reserved b3 vss power/other b4 smi# cmos input b5 init# cmos input b6 vss power/other b7 dpslp# cmos input b8 bpm[1]# common clock output b9 vss power/other b10 preq# common clock input b11 reset# common clock input b12 vss power/other b13 trst# cmos input b14 bclk[1] bus clock input b15 bclk[0] bus clock input b16 vss power/other b17 prochot# open drain output b18 thermda power/other b19 vss power/other table 15. pin listing by pin number pin # pin name signal buffer type direction
package mechanical specifications and pin information 50 datasheet b20 d[7]# source synch input/ output b21 d[3]# source synch input/ output b22 vss power/other b23 d[13]# source synch input/ output b24 d[9]# source synch input/ output b25 vss power/other b26 d[5]# source synch input/ output c1 vss power/other c2 a20m# cmos input c3 rsvd reserved c4 vss power/other c5 test1 test c6 stpclk# cmos input c7 vss power/other c8 bpm[0]# common clock output c9 bpm[3]# common clock input/ output c10 vss power/other c11 tms cmos input c12 tdi cmos input c13 vss power/other c14 bsel[1] cmos output c15 vss power/other c16 bsel[0] cmos output c17 thermtrip# open drain output c18 vss power/other c19 dpwr# common clock input c20 d[8]# source synch input/ output c21 vss power/other c22 dstbp[0]# source synch input/ output c23 dstbn[0]# source synch input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction c24 vss power/other c25 d[15]# source synch input/ output c26 d[12]# source synch input/ output d1 lint0 cmos input d2 vss power/other d3 ferr# open drain output d4 lint1 cmos input d5 vss power/other d6 vcc power/other d7 vss power/other d8 vcc power/other d9 vss power/other d10 vccp power/other d11 vss power/other d12 vccp power/other d13 vss power/other d14 vccp power/other d15 vss power/other d16 vccp power/other d17 vss power/other d18 vcc power/other d19 vss power/other d20 vcc power/other d21 vss power/other d22 vcc power/other d23 vss power/other d24 d[10]# source synch input/ output d25 dinv[0]# source synch input/ output d26 vss power/other e1 psi# cmos output e2 vid[0] cmos output e3 vss power/other e4 pwrgood cmos input e5 vcc power/other table 15. pin listing by pin number pin # pin name signal buffer type direction
datasheet 51 package mechanical specifications and pin information e6 vss power/other e7 vcc power/other e8 vss power/other e9 vcc power/other e10 vss power/other e11 vccp power/other e12 vss power/other e13 vccp power/other e14 vss power/other e15 vccp power/other e16 vss power/other e17 vcc power/other e18 vss power/other e19 vcc power/other e20 vss power/other e21 vcc power/other e22 vss power/other e23 d[14]# source synch input/ output e24 d[11]# source synch input/ output e25 vss power/other e26 rsvd reserved f1 vss power/other f2 vid[1] cmos output f3 vid[2] cmos output f4 vss power/other f5 vss power/other f6 vcc power/other f7 vss power/other f8 vcc power/other f9 vss power/other f10 vccp power/other f11 vss power/other f12 vccp power/other f13 vss power/other f14 vccp power/other f15 vss power/other table 15. pin listing by pin number pin # pin name signal buffer type direction f16 vccp power/other f17 vss power/other f18 vcc power/other f19 vss power/other f20 vcc power/other f21 vss power/other f22 vcc power/other f23 test2 test f24 vss power/other f25 d[21]# source synch input/ output f26 vcca[0] power/other g1 rsvd reserved g2 vss power/other g3 vid[3] cmos output g4 vid[4] cmos output g5 vcc power/other g6 vss power/other g21 vcc power/other g22 vss power/other g23 vss power/other g24 d[22]# source synch input/ output g25 d[17]# source synch input/ output g26 vss power/other h1 rs[0]# common clock input h2 drdy# common clock input/ output h3 vss power/other h4 vid[5] cmos output h5 vss power/other h6 vcc power/other h21 vss power/other h22 vcc power/other h23 d[16]# source synch input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction
package mechanical specifications and pin information 52 datasheet h24 d[20]# source synch input/ output h25 vss power/other h26 d[29]# source synch input/ output j1 vss power/other j2 lock# common clock input/ output j3 bpri# common clock input j4 vss power/other j5 vcc power/other j6 vss power/other j21 vcc power/other j22 vss power/other j23 d[23]# source synch input/ output j24 vss power/other j25 d[25]# source synch input/ output j26 dinv[1]# source synch input/ output k1 rs[1]# common clock input k2 vss power/other k3 hit# common clock input/ output k4 hitm# common clock input/ output k5 vss power/other k6 vccp power/other k21 vss power/other k22 vcc power/other k23 vss power/other k24 dstbn[1]# source synch input/ output k25 d[31]# source synch input/ output k26 vss power/other l1 bnr# common clock input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction l2 rs[2]# common clock input l3 vss power/other l4 defer# common clock input l5 vccp power/other l6 vss power/other l21 vccp power/other l22 vss power/other l23 d[18]# source synch input/ output l24 dstbp[1]# source synch input/ output l25 vss power/other l26 d[26]# source synch input/ output m1 vss power/other m2 dbsy# common clock input/ output m3 trdy# common clock input m4 vss power/other m5 vss power/other m6 vccp power/other m21 vss power/other m22 vccp power/other m23 d[24]# source synch input/ output m24 vss power/other m25 d[28]# source synch input/ output m26 d[19]# source synch input/ output n1 vcca[2] power/other n2 ads# common clock input/ output n3 vss power/other n4 br0# common clock input/ output n5 vccp power/other n6 vss power/other table 15. pin listing by pin number pin # pin name signal buffer type direction
datasheet 53 package mechanical specifications and pin information n21 vccp power/other n22 vss power/other n23 vss power/other n24 d[27]# source synch input/ output n25 d[30]# source synch input/ output n26 vss power/other p1 req[3]# source synch input/ output p2 vss power/other p3 req[1]# source synch input/ output p4 a[3]# source synch input/ output p5 vss power/other p6 vccp power/other p21 vss power/other p22 vccp power/other p23 vccq[0] power/other p24 vss power/other p25 comp[0] power/other input/ output p26 comp[1] power/other input/ output r1 vss power/other r2 req[0]# source synch input/ output r3 a[6]# source synch input/ output r4 vss power/other r5 vccp power/other r6 vss power/other r21 vccp power/other r22 vss power/other r23 d[39]# source synch input/ output r24 d[37]# source synch input/ output r25 vss power/other table 15. pin listing by pin number pin # pin name signal buffer type direction r26 d[38]# source synch input/ output t1 req[4]# source synch input/ output t2 req[2]# source synch input/ output t3 vss power/other t4 a[9]# source synch input/ output t5 vss power/other t6 vccp power/other t21 vss power/other t22 vccp power/other t23 vss power/other t24 dinv[2]# cmos input/ output t25 d[34]# source synch input/ output t26 vss power/other u1 a[13]# source synch input/ output u2 vss power/other u3 adstb[0]# source synch input/ output u4 a[4]# source synch input/ output u5 vcc power/other u6 vss power/other u21 vccp power/other u22 vss power/other u23 d[35]# source synch input/ output u24 vss power/other u25 d[43]# source synch input/ output u26 d[41]# source synch input/ output v1 vss power/other v2 a[7]# source synch input/ output v3 a[5]# source synch input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction
package mechanical specifications and pin information 54 datasheet v4 vss power/other v5 vss power/other v6 vcc power/other v21 vss power/other v22 vcc power/other v23 d[36]# source synch input/ output v24 d[42]# source synch input/ output v25 vss power/other v26 d[44]# source synch input/ output w1 a[8]# source synch input/ output w2 a[10]# source synch input/ output w3 vss power/other w4 vccq[1] power/other w5 vcc power/other w6 vss power/other w21 vcc power/other w22 vss power/other w23 vss power/other w24 dstbp[2]# source synch input/ output w25 dstbn[2]# source synch input/ output w26 vss power/other y1 a[12]# source synch input/ output y2 vss power/other y3 a[15]# source synch input/ output y4 a[11]# source synch input/ output y5 vss power/other y6 vcc power/other y21 vss power/other y22 vcc power/other y23 d[45]# source synch input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction y24 vss power/other y25 d[47]# source synch input/ output y26 d[32]# source synch input/ output table 15. pin listing by pin number pin # pin name signal buffer type direction
datasheet 55 package mechanical specifications and pin information 4.2 alphabetical signals reference table 16. signal description (sheet 1 of 8) name type description a[31:3]# input/ output a[31:3]# (address) define a 2 32 -byte physical memory address space. in sub-phase 1 of the address phase, these pins transmit the address of a transaction. in su b-phase 2, these pins transmit transaction type information. these signals must connect the appropriate pins of both agents on the intel? celeron? m processor fsb. a[31:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0] #. address signals are used as straps which are sampled befo re reset# is deasserted. a20m# input if a20m# (address-20 mask) is asserted, the processor masks physical address bit 20 (a20#) be fore looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates th e 8086 processor's address wrap- around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/outp ut write instruction, it must be valid along with the trdy# assertion of the corresponding input/ output write bus transaction. ads# input/ output ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[31:3]# and req[4:0]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, addr ess decode, internal sn oop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latch a[31:3]# and req[4:0]# on their rising and falling edges. strobes are associated with signals as shown below. bclk[1:0] input the differential pair bclk (bus cl ock) determines the fsb frequency. all fsb agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are specified with respect to the rising edge of bclk0 crossing v cross . bnr# input/ output bnr# (block next reques t) is used to assert a bus stall by any bus agent who is unable to accept ne w bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. bpm[2:0]# bpm[3] output input/ output bpm[3:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpm[3:0]# should connect the appropriate pins of al l celeron m fsb agents.this includes debug or performance monitoring tools. signals associated strobe req[4:0]#, a[16:3]# adstb[0]# a[31:17]# adstb[1]#
package mechanical specifications and pin information 56 datasheet bpri# input bpri# (bus priority request) is used to arbitrate for ownership of the fsb. it must connect the approp riate pins of both fsb agents. observing bpri# active (as asserted by the priority agent) causes the other agent to stop issuing ne w requests, unless such requests are part of an ongoing locked op eration. the priority agent keeps bpri# asserted until all of its requ ests are completed, then releases the bus by deasserting bpri#. br0# input/ output br0# is used by the processor to request the bus. the arbitration is done between celeron m (sym metric agent) and intel? 915/910 express chipset and intel? 852/855 chipset families (high priority agent). bsel[1:0] output the bsel[1:0] signals are used to select the frequency of the processor input clock(bc lk[1:0]. these signals should be connected to the clock chip and intel 915gm/gms/pm & 910gml express chipsets on the platform. these signals must be left unconnected on intel 852/855 chipset family-based platforms. comp[3:0] analog comp[3:0] must be terminated on the system board using precision (1% tolerance) resistors. d[63:0]# input/ output d[63:0]# (data) are the data signals. these si gnals provide a 64-bit data path between the fsb agents, and must connect the appropriate pins on both agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumpe d signals and will thus be driven four times in a common clock period. d[ 63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dinv# . furthermore, the dinv# pins dete rmine the polarity of the data signals. each group of 16 data signals corresponds to one dinv# signal. when the dinv# signal is active, the corresponding data group is inverted and ther efore sampled active high. dbr# output dbr# (data bus reset) is used on ly in processor systems where no debug port is implemented on the sy stem board. dbr# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port is implemen ted in the system, dbr# is a no connect in the system. dbr# is not a processor signal. table 16. signal descript ion (sheet 2 of 8) name type description quad-pumped signal groups data group dstbn#/ dstbp# dinv# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3
datasheet 57 package mechanical specifications and pin information dbsy# input/ output dbsy# (data bus busy) is asserted by the agent responsible for driving data on the fsb to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pi ns on both fsb agents. defer# input defer# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addresse d memory or inpu t/output agent. this signal must connect the appr opriate pins of both fsb agents. dinv[3:0]# input/ output dinv[3:0]# (data bus inversion) are source synchronous and indicate the polarity of the d[ 63:0]# signals. the dinv[3:0]# signals are activated when the data on the data bus is inverted. the bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. dpslp# input dpslp# when asserted on the platform causes the processor to transition from the sleep state to the deep sleep state. in order to return to the sleep st ate, dpslp# must be deasserted. dpslp# is driven by the ich-m component and also connects to the mch-m component. dpwr# input dpwr# is a control signal from th e intel chipset used to reduce power on the celeron m data bus input buffers. drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be de asserted to insert idle clocks. this signal must connect the appr opriate pins of both fsb agents. dstbn[3:0] # input/ output data strobe used to latch in d[63:0]#. table 16. signal description (sheet 3 of 8) name type description dinv[3:0]# assignment to data bus bus signal data bus signals dinv[3]# d[63:48]# dinv[2]# d[47:32]# dinv[1]# d[31:16]# dinv[0]# d[15:0]# signals associated strobe d[15:0]#, dinv[0]# dstbn[0]# d[31:16]#, dinv[1]# dstbn[1]# d[47:32]#, dinv[2]# dstbn[2]# d[63:48]#, dinv[3]# dstbn[3]#
package mechanical specifications and pin information 58 datasheet dstbp[3:0]# input/ output data strobe used to latch in d[63:0]#. ferr#/pbe# output ferr# (floating-point error)pbe#(pending break event) is a multiplexed signal and its meaning is qualified with stpclk#. when stpclk# is not asserted, ferr#/pb e# indicates a floating point when the processor detects an unma sked floating-point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms-dos*-type floating-point error reporting. when stpclk# is asserted, an assertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to th e normal state. when ferr#/pbe# is asserted, indicating a break event, it will remain asserted until stpclk# is deasserted. assertion of preq# when stpclk# is active will al so cause an ferr# break event. for additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to volume 3 of the intel? architecture software developer?s manual and the intel? processor identification and cpuid instruction application note. gtlref input gtlref determines the signal reference level for agtl+ input pins. gtlref should be set at 2/3 v ccp . gtlref is used by the agtl+ receivers to determine if a signal is a logical 0 or logical 1. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation results. either fs b agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by re asserting hit# and hitm# together. ierr# output ierr# (internal error) is asserted by a processor as th e result of an internal error. assertion of ie rr# is usually accompanied by a shutdown transaction on the fsb. this transaction may optionally be converted to an external error si gnal (e.g., nmi) by system core logic. the processor will keep ierr # asserted until the assertion of reset#, binit#, or init#. ignne# input ignne# (ignore numeric error) is as serted to force the processor to ignore a numeric error and continue to execute noncontrol floating- point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floati ng-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in contro l register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an input/ou tput write instruction, it must be valid along with the trdy# assert ion of the corre sponding input/ output write bus transaction. table 16. signal descript ion (sheet 4 of 8) name type description signals associated strobe d[15:0]#, dinv[0]# dstbp[0]# d[31:16]#, dinv[1]# dstbp[1]# d[47:32]#, dinv[2]# dstbp[2]# d[63:48]#, dinv[3]# dstbp[3]#
datasheet 59 package mechanical specifications and pin information init# input init# (initialization), wh en asserted, resets in teger registers inside the processor without affecting its in ternal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchrono us signal. however, to ensure recognition of this signal following an input/output wr ite instruction, it must be valid along with the t rdy# assertion of the corresponding input/output write bus transaction. init# must connect the appropriate pins of both fsb agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). itp_clk[1:0] input itp_clk[1:0] are copies of bclk that are used only in processor systems where no debug port is im plemented on the system board. itp_clk[1:0] are used as bclk[1 :0] references fo r a debug port implemented on an interposer. if a debug port is im plemented in the system, itp_clk[1:0] are no connects in the system. these are not processor signals. lint[1:0] input lint[1:0] (local apic interrupt) must connect the appropriate pins of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interru pt request signal, and lint1 becomes nmi, a nonmaskable interru pt. intr and nmi are backward compatible with the signals of thos e names on the celeron processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/ intr or lint[1:0]. because the ap ic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# input/ output lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of both fsb agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first tran saction to the end of the last transaction. when the priority agent asserts bp ri# to arbitrate for ownership of the fsb, it will wait until it observes lock# deasserted. this enables symmetric agents to retain owners hip of the fsb throughout the bus locked operation and ensure the atomicity of lock. prdy# output probe ready signal used by debu g tools to determine processor debug readiness. preq# input probe request signal used by debu g tools to request debug operation of the processor. prochot# output prochot# (processor hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit has been activated, if enabled. see chapter 5 for more details. psi# output processor power status indicator (psi ) signal. this sign al is asserted when the processor is in a lower state (deep sleep). see section 2.1.4 for more details. table 16. signal description (sheet 5 of 8) name type description
package mechanical specifications and pin information 60 datasheet pwrgood input pwrgood (power good) is a pr ocessor input. the processor requires this signal to be a clean indication th at the clocks and power supplies are stable and with in their specifications. clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. the pwrgood signal must be supplied to the proces sor; it is used to protect internal circuits against vo ltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request co mmand) must connect the appropriate pins of both fsb agents. they are asse rted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb[0]#. reset# input asserting the reset# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least two milliseconds after v cc and bclk have reached their proper specifications. on observing active reset#, both fsb agents will deassert their outputs within two clocks. all processor straps must be valid within the specified setup ti me before reset# is deasserted. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current tr ansaction), and must connect the appropriate pins of both fsb agents. rsvd reserved /no connect these pins are reserved and must be left unco nnected on the board. however, it is recommende d that routing channels to these pins on the board be kept op en for possible future use. slp# input slp# (sleep), when asserted in stop-grant state, causes the processor to enter the sleep state. during sleep state, the processor stops providing internal clock sign als to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will recognize only assertion of the reset# signal, de assertion of slp#, and removal of the bclk input while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop -grant state, restarting its internal clock signals to the bus and processor core units. if dpslp# is asserted while in the sleep state, the processor will exit the sleep state and transition to the deep sleep state. smi# input smi# (system manageme nt interrupt) is asse rted asynchronously by system logic. on accepting a system mana gement interrupt, the processor saves the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program ex ecution from the smm handler. if smi# is asserted during the de assertion of reset# the processor will tristate its outputs. table 16. signal descript ion (sheet 6 of 8) name type description
datasheet 61 package mechanical specifications and pin information stpclk# input stpclk# (stop clock), when asserted, causes the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units exce pt the fsb and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. wh en stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck input tck (test clock) provides the cloc k input for the processor test bus (also known as the te st access port). tdi input tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. test1, test2 input test1 and test2 must have a stuffing option of separate pull down resistors to v ss . thermda other thermal diode anode. thermdc other thermal diode cathode. thermtrip# output the processor protects itself from catastrophic overheating by use of an internal thermal sensor. this se nsor is set well above the normal operating temperature to ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds approximately 125c. this is signalled to the system by the thermtrip# (thermal trip) pin. tms input tms (test mode select) is a jtag sp ecification support signal used by debug tools. trdy# input trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of both fsb agents. trst# input trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. v cc input processor core power supply. v cca [3:0] input v cca provides isolated power for the internal processor core pll?s. v ccp input processor i/o power supply. v ccq [1:0] input quiet power supply for on die comp circuitry. these pins should be connected to v ccp on the motherboard. however, these connections should enable addition of decoupling on the v ccq lines if necessary. table 16. signal description (sheet 7 of 8) name type description
package mechanical specifications and pin information 62 datasheet v ccsense output v ccsense is an isolated low impedance connection to processor core power (v cc ). it can be used to sense or measure power near the silicon with little noise. vid[5:0] output vid[5:0] (voltage id) pins are used to support automatic selection of power supply voltages (v cc ). unlike some previous generations of processors, these are cmos signals that are driven by the celeron m processor. the voltage supply for thes e pins must be valid before the vr can supply v cc to the processor. conversely, the vr output must be disabled until the voltage suppl y for the vid pins becomes valid. the vid pins are needed to support the processor voltage specification variations. see ta b l e 1 for definitions of these pins. the vr must supply the voltage that is requested by the pins, or disable itself. v sssense output v sssense is an isolated low impedance connection to processor core v ss . it can be used to sense or meas ure ground near the silicon with little noise. table 16. signal descript ion (sheet 8 of 8) name type description
datasheet 63 thermal specifications and design considerations 5 thermal specifications and design considerations the celeron m processor requires a thermal so lution to maintain temperatures within operating limits as set forth in ta b l e 1 7 . any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. as processor technology changes, thermal management becomes increasingly cruc ial when building computer systems. maintaining the proper thermal environmen t is key to reliable, long-term system operation. a complete thermal solution in cludes both component and system level thermal management features. component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. the solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. a typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct die attachment. a secondary fan, or air from the processor fan, may also be used to cool other platform components or lower the internal ambient temperature within the system. to allow for the optimal operation and long-term reliability of intel processor-based systems, the system/processor thermal solution should be designed such that the processor must remain within the minimum and maximum junction temperature (tj) specifications at the corresponding ther mal design power (tdp) value listed in ta b l e 1 7 . thermal solutions not design to provide this level of thermal capability may affect the long-term reliability of the processor and system. the maximum junction temperature is defined by an activation of the processor intel? thermal monitor. refer to section 5.1.3 for more details. analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the tdp indicated in ta b l e 1 7 . the intel thermal monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the tdp recommendation for a sustained period of time. for more details on the usage of this feature, refer to section 5.1.3 . in all cases, the intel thermal monitor feature must be enabled for the proce ssor to remain within specification.
thermal specifications and design considerations 64 datasheet table 17. power specifications for th e celeron m processor (sheet 1 of 2) symbol processor number core frequency & voltage thermal design power unit notes tdp 390 1.7 ghz & v cc2 27 w at 100c, notes 1, 4,5,6 380 1.6 ghz & v cc2 21 370 1.5 ghz & v cc2 21 360j 1.4 ghz & v cc2 21 360 1.4 ghz & 1.260 v 21 350j 1.3 ghz & v cc2 21 350 1.3 ghz & 1.260 v 21 383 1.1 ghz & v cc3 5.5 373 1.0 ghz & v cc3 5.5 353 900 mhz & 0.940 v 5.0 symbol processor number parameter min typ max unit notes p ah, p sgnt auto halt, stop grant power at: w at 50c, note 2,5,6 390 v cc2 11.6 380 v cc2 11.6 370 v cc2 11.6 360j v cc2 11.6 360 1.260 v 11.6 350j v cc2 11.6 350 1.260 v 11.6 383 v cc3 1.9 373 v cc3 1.9 353 0.940 v 1.9 p slp sleep power at: w at 50c, note 2,5,6 390 v cc2 11.3 380 v cc2 11.3 370 v cc2 11.3 360j v cc2 11.3 360 1.260 v 11.3 350j v cc2 11.3 350 1.260 v 11.3 383 v cc3 1.8 373 v cc3 1.8 353 0.940 v 1.8
datasheet 65 thermal specifications and design considerations notes: 1. the thermal design power (tdp) specification should be used to design the pr ocessor thermal solution. the tdp is not the maximum theoretical power the processor can dissipate. 2. not 100% tested. these power specifications are dete rmined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. as measured by the on-die intel thermal monitor. the intel thermal monitor?s automatic mode is used to indicate that the maximum t j has been reached. refer to section 5.1 for more details. 4. the intel thermal monitor automatic mode must be enabled for the proces sor to operate within specifications. 5. intel processor numbers are not a measure of perf ormance. processor number s differentiate features within each processor fa mily, not across different processor families. se e www.intel.com/products/ processor_number for details. 6. see ta b l e 4 for v cc2 and v cc3. 5.1 thermal specifications 5.1.1 thermal diode the celeron m processor incorporates two me thods of monitoring die temperature, the intel thermal monitor and the thermal diode. the intel thermal monitor (detailed in section 5.1 ) must be used to determine when the maximum specified processor junction temperature has been reached. the second method, the thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. the thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but cannot be used to indicate that the maximum t j of the processor has been reached. when using the thermal diode, a temperature offset value must be read from a processor model specific register (msr) and applied. see section 5.1.2 for more details. please see section 5.1.3 for thermal diode usage recommendation when the prochot# signal is not asserted. ta b l e 1 8 and ta b l e 1 9 provide the diode interface and specifications. note: the reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, will not ne cessarily reflect the temperature of the hottest location on the die. this is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the loca tion of the thermal diode and the hottest location on the die, and time based variat ions in the die temperature measurement. time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the t j temperature can change. p dslp deep sleep power at: w at 35c, note 2,5,6 390 v cc2 8.8 380 v cc2 8.8 370 v cc2 8.8 360j v cc2 8.8 360 1.260 v 8.8 350j v cc2 8.8 350 1.260 v 8.8 383 v cc3 1.4 373 v cc3 1.4 353 0.940 v 1.4 t j junction temperature 0 100 cnotes 3, 4 table 17. power specifications for th e celeron m processor (sheet 2 of 2)
thermal specifications and design considerations 66 datasheet offset between the thermal diode based te mperature reading and the intel thermal monitor reading may be characterized using the intel thermal monitor?s automatic mode activation of thermal control circuit. this temperature offset must be taken into account when using the processor therma l diode to implement power management events. 5.1.2 thermal diode offset a temperature offset value (specified as toffset in ta b l e 1 9 ) will be programmed into a celeron m processor model specific register (m sr). this offset is determined by using a thermal diode ideality factor mean value of n = 1.0022 (shown in ta b l e 1 9 ) as a reference. this offset must be applied to the junction temperature read by the thermal diode. any temperature adjustments due to differences between the reference ideality value of 1.0022 and the default ideality valu es programmed into the on-board thermal sensors, will have to be made before the above offset is applied. notes: 1. intel does not support or re commend operation of the thermal diode under reverse bias. intel does not support or recommend operation of the thermal diode when the processor power supplies are not within th eir specified tolerance range. 2. characterized at 100c. 3. not 100% tested. specified by design/characterization. 4. the ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by the diode equation: i fw =i s *(e (qv d /nkt) - 1 ) where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). value shown in the table is not the celeron m processor thermal diode ideality factor. it is a reference value used to calculate the ce leron m thermal diode temperature offset. 5. the series resistance, r t , is provided to allow for a mo re accurate measurement of the diode junction temperature. r t as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. r t can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode ther mal sensors as exemplified by the equation: t error = [r t *(n-1)*i fwmin ]/[(no/q)*ln n] 6. offset value is programmed in processor model specific register. table 18. thermal diode interface signal name pin/ball nu mber signal description thermda b18 thermal diode anode thermdc a18 thermal diode cathode table 19. thermal diode specification symbol parameter min typ max unit notes i fw forward bias current 5 300 a note 1 to ff s e t thermal diode temperature offset -4 11 c 2, 6 n reference diode ideality factor used to calculate temperature offset 1.0022 notes 2, 3, 4 r t series resistance 3.06 2, 3, 5
datasheet 67 thermal specifications and design considerations 5.1.3 intel? thermal monitor the intel thermal monitor helps control the processor temperature by activating the tcc when the processor silicon reaches its maximum operating temperature. the temperature at which intel thermal monitor activates the thermal control circuit is not user configurable and is not software visi ble. bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the tcc is active. with a properly designed and characterized th ermal solution, it is anticipated that the tcc would only be activated for very shor t periods of time when running the most power intensive applications. the processo r performance impact due to these brief periods of tcc activation is expected to be so minor that it would not be detectable. an under-designed thermal solution that is not able to prevent excessive activation of the tcc in the anticipated ambient environment may cause a noticeable performance loss, and may affect the long-term re liability of the processor. in addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the tcc is active continuously. the intel thermal monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. the intel thermal monitor uses two modes to activate the tcc: automatic mode and on-d emand mode. if both modes are activated, automatic mode takes precedence. the intel thermal monitor automatic mode must be enabled via bios for the processor to be operating within specifications. the automatic mode called intel thermal monitor 1 this mode is selected by writing values to the model specific registers (msrs) of the processor. after automatic mode is enabled, the tcc will activate only when the internal die temperature reaches the maximum allowed value for operation. when intel thermal monitor 1 is enabled, and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. once the temperature has returned to a non- critical level, modulation ceases and tcc go es inactive. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near the trip point. the duty cycle is factory configured and cannot be modified. also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. processor performance will be decreased by the same amount as the duty cy cle when the tcc is active, however, with a properly designed and characterized ther mal solution the tcc most likely will never be activated, or only will be activated briefly during the most power intensive applications. the tcc may also be activated via on-demand mode. if bit 4 of the acpi intel thermal monitor control register is written to a 1, the tcc will be activated immediately, independent of the processor temperature. when using on-demand mode to activate the tcc, the duty cycle of the clock modulation is programmable via bits 3:1 of the same acpi intel thermal monitor control register. in automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the tcc via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. an external signal, prochot# (processor hot) is asserted when the processor detects that its temperature is above the therma l trip point. bus snooping and interrupt latching are also active while the tcc is active. note: prochot# will not be asserted when the proc essor is in the stop grant, sleep, deep sleep, and deeper sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction
thermal specifications and design considerations 68 datasheet temperature within the 100c (maximum) sp ecification. if the platform thermal solution is not able to maintain the pr ocessor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. if the processor enters one of th e above low power states with prochot# already asserted, prochot# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. if automatic mode is disabled, the processo r will be operating out of specification. regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximatel y 125c. at this point the fsb signal thermtrip# will go active. thermtrip# ac tivation is independent of processor activity and does not generate any bus cy cles. when thermtrip# is asserted, the processor core voltage must be shut down within a time specified in chapter 3 .

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